The present invention relates to the digital interface for multiple analog to digital converters (ADCs) or digital to analog converters (DACs), particularly for transferring sampled signal data at higher rates over fewer data ports at the digital interface.
A typical digital interface for multiple ADCs operating in parallel includes the same number of data ports for transferring signal samples. Each ADC digitally samples a corresponding input analog signal at a sample rate and a number of bits per sample, or sample width, to produce the signal samples. The bit rate is the product of the sample rate and the number of bits per sample. In typical designs, the data transfer rate of the data port is the same as the ADC bit rate. In flexible ADC systems, the ADC can be configured to operate at a selected sample rate within a range of possible sample rates, often in response to an externally supplied sample clock. The data ports can also operate at different data transfer rates so that they match the ADC bit rates. The bits of the signal samples are serialized and transmitted over the data port at the same rate that they are generated but with a fixed latency.
In general, the sample rate of the ADC is set to at least the Nyquist rate for the input analog signal to produce samples free of aliasing. The Nyquist rate is two times the bandwidth of the input analog signal. In some situations, an input analog signal having a narrower bandwidth can allow the sample rate of the ADC to be lower than the ADC's maximum sample rate. The data port connected to the ADC will transfer the bits at a lower rate than the maximum data transfer rate. Even though they are operating below capacity, the data ports often consume the same amount of power. Furthermore, the number of I/O pins remains the same so that the design complexity and related system costs are the same as when the bandwidth is fully utilized or when the ADCs are operating at their maximum rate.
An analogous situation exists for DAC interfaces. For example, signal samples representing multiple signals that have been processed by a digital signal processor are transferred across a digital interface to multiple DACs where they will be converted to multiple analog signals. The digital interface includes a data port for each DAC. When the product of the sample rate and number bits per sample results in a lower bit rate than the maximum data transfer rate per port, there is excess data transfer bandwidth at the digital interface. Again, there are power consumption, design complexity and system costs related to maintaining the same number of data ports having unused bandwidth.
Another approach for transferring data from multiple ADCs or to multiple DACs is to serialize the signal samples for a high speed serial data link. Existing industry standards such as PCI Express, aimed at microprocessors or interface devices, add overhead and complexity to the serialized data that are unnecessary for a simple continuous, constant bandwidth data stream. The industry standard entitled “JEDEC Standard for Serial Interface for Data Converters JESD204,” published by the JEDEC Solid State Technology Association in April 2006, specifies architectures and data formats for transfer of signal samples over high speed serial data links between data converters and digital logic devices, referred to as 8b/10b SerDes. The JEDEC Standard describes arranging the bits of signal samples into 8-bit data words. Each 8-bit data word is mapped to a 10-bit symbol in accordance with an 8b/10b code (IEEE Standard 802.3-2002). The 10-bit symbols are then serialized for transfer over the data link. For signal samples having a data width greater than 8 bits, the bits are sequentially arranged into 8-bit data words. For instance, a 12-bit signal sample would have 8 bits in a first word and 4 bits in a second word. The next 12-bit signal sample would have 4 bits in the second word and 8 bits in a third word and so forth. For multiple ADCs or DACs in parallel, the bits of signal samples corresponding to each ADC or DAC are arranged sequentially in a frame of 8-bit data words, where a frame includes the data words generated during one sample period. The 8b/10b encoding of each 8-bit word forms a frame of 10-bit symbols that are serialized and transferred over the data link. On the receiver side, the received serial data stream is deserialized to reconstruct the 10-bit symbols that are 8b/10b decoded to regenerate the 8-bit words of each frame. The bits corresponding to the sample width of each signal sample are extracted from the 8-bit words to reconstruct the signal samples for the corresponding ADC or DAC. The JEDEC Standard specifies a range of gross data transfer rates from 0.3125 to 3.125 gigabits per second (Gbps).
The JEDEC SerDes architecture has the complexity and overhead of 8b/10b encoding at the transmit side and 8b/10b decoding at the receive side. The fixed 8-bit word size also adds complexity for data converters whose sample width is not equal to 8 bits and/or have multiple ADCs or multiple DACs operating in parallel. The JEDEC SerDes architecture is applicable to high speed serial data links for longer distances (up to 20 cm at 3.125 Gbps), however it is more costly and requires more power.
In a system having multiple ADCs or multiple DACs, there is a need for a digital interface that increases power efficiency, reduces system complexity and reduces the cost of the system. There is a need for a digital interface that exploits unused bandwidth of the data ports to realize these improvements.